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K6T1008V2C, K6T1008U2C Family
Document Title
128K x8 bit Low Power and Low Voltage CMOS Static RAM
CMOS SRAM
Revision History
Revision No. History
0.0 1.0 Initial draft Finalize - Increased ISB, IDR Commercial part = 10A Industrial part = 20A Revise - Change speed bin KM68V1000C Family: 70/85ns 70/100ns KM68U1000C Family: 70/100ns 85/100ns - Improved operating current: 40mA 35mA - Improved power dissipation PD: 0.7W 1.0W - Improved standby current Extended/Industrial: 20 10A - VIL: 0.4V 0.6V
Draft Data
July 3, 1996 December 16, 1996
Remark
Preliminary Final
2.0
November 25, 1997
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 2.0 November 1997
K6T1008V2C, K6T1008U2C Family
128K x8 bit Low Power and Low Voltage CMOS Static RAM
FEATURES
* Process Technology: 0.4m CMOS * Organization: 128K x8 * Power Supply Voltage: K6T1008V2C family: 3.0~3.6V K6T1008U2C family: 2.7~3.3V * Low Data Retention Voltage: 2V(Min) * Three state output and TTL Compatible * Package Type: 32-SOP-525, 32-TSOP1-0820F/R, 32-TSOP1-0813.4F/R
CMOS SRAM
GENERAL DESCRIPTION
The K6T1008V2C and K6T1008U2C families are fabricated by SAMSUNGs advanced CMOS process technology. The families support various operating temperature ranges and have various package types for user flexibility of system design. The families also supports low data retention voltage for battery back-up operation with low data retention current.
PRODUCT FAMILY
Power Dissipation Product Family K6T1008V2C-B K6T1008U2C-B K6T1008V2C-D K6T1008U2C-D K6T1008V2C-F K6T1008U2C-F Industrial(-40~85C) Extended(-25~85C) Operating Temperature Vcc Range 3.0~3.6V 2.7~3.3V 3.0~3.6V 2.7~3.3V 3.0~3.6V 2.7~3.3V Speed 70/100ns 85/100ns 70/100ns 85/100ns 70/100ns 85/100ns 10A 35mA 32-SOP 32-TSOP1-F/R 32-sTSOP1-F/R Standby (ISB1, Max) Operating (ICC2, Max) PKG Type
Commercial(0~70C)
PIN DESCRIPTION
A11 A9 A8 A13 WE VCC CS2 A15 A15 VCC CS2 NC A16 WE A14 A12 A13 A7 A6 A8 A5 A9 A4 A11 OE A4 A5 A6 CS1 A7 I/O8 A12 A14 I/O7 A16 NC I/O6 VCC I/O5 A15 CS2 I/O4 WE A13 A8 A9 A11 A10 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS I/O4 I/O5 I/O6 I/O7 I/O8 CS1 A10 OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CS1 I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 A3
FUNCTIONAL BLOCK DIAGRAM
Clk gen. Precharge circuit.
N.C A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26
A4 A5 A6 A7 A8 A12 A13 A14 A15 A16
32-TSOP 32-STSOP Type1-Forward
VCC VSS Memory array 1024 rows 128x8 columns
Row select
32-SOP
25 24 23 22 21 20 19 18 17
I/O1 I/O8
32-TSOP 32-STSOP Type1-Reverse
Data cont
I/O Circuit Column select
A10 A0
A1
A2 A3 A9
A11
Name
CS1, CS2 OE WE A0~A16 I/O1~I/O8 Vcc Vss N.C
Function
Chip Select Inputs Output Enable Input Write Enable Input Address Inputs Data Inputs/Outputs Power Ground No Connection
CS1 CS2 WE OE
Control logic
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
Revision 2.0 November 1997
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K6T1008V2C, K6T1008U2C Family
PRODUCT LIST
Commercial Temperature Products (0~70C) Part Name
K6T1008V2C-GB70 K6T1008V2C-GB10 K6T1008V2C-TB70 K6T1008V2C-TB10 K6T1008V2C-RB70 K6T1008V2C-RB10 K6T1008U2C-GB85 K6T1008U2C-GB10 K6T1008U2C-TB85 K6T1008U2C-TB10 K6T1008U2C-RB85 K6T1008U2C-RB10 K6T1008V2C-YB70 K6T1008V2C-YB10 K6T1008V2C-NB70 K6T1008V2C-NB10 K6T1008U2C-YB85 K6T1008U2C-YB10 K6T1008U2C-NB85 K6T1008U2C-NB10
CMOS SRAM
Industrial Temperature Products (-40~85C) Part Name
K6T1008V2C-GF70 K6T1008V2C-GF10 K6T1008V2C-TF70 K6T1008V2C-TF10 K6T1008V2C-RF70 K6T1008V2C-RF10 K6T1008U2C-GF85 K6T1008U2C-GF10 K6T1008U2C-TF85 K6T1008U2C-TF10 K6T1008U2C-RF85 K6T1008U2C-RF10 K6T1008V2C-YF70 K6T1008V2C-YF10 K6T1008V2C-NF70 K6T1008V2C-NF10 K6T1008U2C-YF85 K6T1008U2C-YF10 K6T1008U2C-NF85 K6T1008U2C-NF10
Extended Temperature Products (-25~85C) Part Name
K6T1008V2C-GD70 K6T1008V2C-GD10 K6T1008V2C-TD70 K6T1008V2C-TD10 K6T1008V2C-RD70 K6T1008V2C-RD10 K6T1008U2C-GD85 K6T1008U2C-GD10 K6T1008U2C-TD85 K6T1008U2C-TD10 K6T1008U2C-RD85 K6T1008U2C-RD10 K6T1008V2C-YD70 K6T1008V2C-YD10 K6T1008V2C-ND70 K6T1008V2C-ND10 K6T1008U2C-YD85 K6T1008U2C-YD10 K6T1008U2C-ND85 K6T1008U2C-ND10
Function
32-SOP, 70ns, 3.3V 32-SOP, 100ns, 3.3V 32-TSOP F, 70ns, 3.3V 32-TSOP F, 100ns, 3.3V 32-TSOP R, 70ns, 3.3V 32-TSOP R, 100ns, 3.3V 32-SOP, 85ns, 3.0V 32-SOP, 100ns, 3.0V 32-TSOP F, 85ns, 3.0V 32-TSOP F, 100ns, 3.0V 32-TSOP R, 85ns, 3.0V 32-TSOP R, 100ns, 3.0V 32-sTSOP F, 70ns, 3.3V 32-sTSOP F, 100ns, 3.3V 32-sTSOP R, 70ns, 3.3V 32-sTSOP R, 100ns, 3.3V 32-sTSOP F, 85ns, 3.0V 32-sTSOP F, 100ns, 3.0V 32-sTSOP R, 85ns, 3.0V 32-sTSOP R, 100ns, 3.0V
Function
32-SOP, 70ns, 3.3V 32-SOP, 100ns, 3.3V 32-TSOP F, 70ns, 3.3V 32-TSOP F, 100ns, 3.3V 32-TSOP R, 70ns, 3.3V 32-TSOP R, 100ns, 3.3V 32-SOP, 85ns, 3.0V 32-SOP, 100ns, 3.0V 32-TSOP F, 85ns, 3.0V 32-TSOP F, 100ns, 3.0V 32-TSOP R, 85ns, 3.0V 32-TSOP R, 100ns, 3.0V 32-sTSOP F, 70ns, 3.3V 32-sTSOP F, 100ns, 3.3V 32-sTSOP R, 70ns, 3.3V 32-sTSOP R, 100ns, 3.3V 32-sTSOP F, 85ns, 3.0V 32-sTSOP F, 100ns, 3.0V 32-sTSOP R, 85ns, 3.0V 32-sTSOP R, 100ns, 3.0V
Function
32-SOP, 70ns, 3.3V 32-SOP, 100ns, 3.3V 32-TSOP F, 70ns, 3.3V 32-TSOP F, 100ns, 3.3V 32-TSOP R, 70ns, 3.3V 32-TSOP R, 100ns, 3.3V 32-SOP, 85ns, 3.0V 32-SOP, 100ns, 3.0V 32-TSOP F, 85ns, 3.0V 32-TSOP F, 100ns, 3.0V 32-TSOP R, 85ns, 3.0V 32-TSOP R, 100ns, 3.0V 32-sTSOP F, 70ns, 3.3V 32-sTSOP F, 100ns, 3.3V 32-sTSOP R, 70ns, 3.3V 32-sTSOP R, 100ns, 3.3V 32-sTSOP F, 85ns, 3.0V 32-sTSOP F, 100ns, 3.0V 32-sTSOP R, 85ns, 3.0V 32-sTSOP R, 100ns, 3.0V
FUNCTIONAL DESCRIPTION
CS1
H X1) L L L
CS2
X
1)
OE
X
1)
WE
X
1)
I/O Pin
High-Z High-Z High-Z Dout Din
Mode
Deselected Deselected Output Disabled Read Write
Power
Standby Standby Active Active Active
L H H H
X1) H L X
1)
X1) H H L
1. X means dont care(Must be in high or low status.)
ABSOLUTE MAXIMUM RATINGS1)
Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Power Dissipation Storage temperature Operating Temperature Symbol VIN,VOUT VCC PD TSTG TA Ratings -0.5 to VCC+0.5 -0.3 to 4.6 1.0 -65 to 150 0 to 70 -25 to 85 -40 to 85 Soldering temperature and time TSOLDER 260C, 10sec (Lead Only) Unit V V W C C C C Remark K6T1008V2C-B/K6T1008U2C-B K6T1008V2C-D/K6T1008U2C-D K6T1008V2C-F/K6T1008U2C-F -
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
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Revision 2.0 November 1997
K6T1008V2C, K6T1008U2C Family
RECOMMENDED DC OPERATING CONDITIONS1)
Item Supply voltage Ground Input high voltage Input low voltage Symbol Vcc Vss VIH VIL Product K6T1008V2C Family K6T1008U2C Family All Family K6T1008V2C, K6T1008U2C Family K6T1008V2C, K6T1008U2C Family Min 3.0 2.7 0 2.2 -0.3
3)
CMOS SRAM
Typ 3.3 3.0 0 Max 3.6 3.3 0 Vcc+0.32) 0.6 Unit V V V V
1. Commercial Product: TA=0 to 70C, unless otherwise specified Extended Product: TA=-25 to 85C, unless otherwise specified Industrial Product: TA=-40 to 85C, unless otherwise specified 2. Overshoot: VCC+3.0V in case of pulse width 30ns 3. Undershoot: -3.0V in case of pulse width 30ns 4. Overshoot and undershoot is sampled, not 100% tested.
CAPACITANCE1) (f=1MHz, TA=25C)
Item Input capacitance Input/Output capacitance
1. Capacitance is sampled, not 100% tested
Symbol CIN CIO
Test Condition VIN=0V VIO=0V
Min -
Max 6 8
Unit pF pF
DC AND OPERATING CHARACTERISTICS
Item Input leakage current Output leakage current Operating power supply Average operating current Symbol ILI ILO ICC ICC1 ICC2 Output low voltage Output high voltage Standby Current(TTL) Standby Current(CMOS) VOL VOH ISB ISB1 VIN=Vss to Vcc CS1=VIH or CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIL or VIH, Read Cycle time=1s, 100% duty, IIO=0mA, CS10.2V, CS2VCC-0.2V, VIN0.2V or VINVCC-0.2V Read Write 2.2 Test Conditions Min -1 -1 Typ 2 1.5 10 25 0.3 Max 1 1 5 5 15 35 0.4 0.3 10 mA V V mA A Unit A A mA mA
Cycle time=Min, 100% duty, IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIL or VIH
IOL=2.1mA IOH=-1.0mA CS1=VIH, CS2=VIL, Other inputs=VIL or VIH CS1Vcc-0.2V, CS2Vcc-0.2V or CS20.2V, Other inputs=0~Vcc
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Revision 2.0 November 1997
K6T1008V2C, K6T1008U2C Family
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Input/Output Reference)
Input pulse level: 0.4 to 2.2V Input rising and falling time: 5ns Input and output reference voltage:1.5V Output load(see right): CL=100pF+1TTL CL1)
CMOS SRAM
1. Including scope and jig capacitance
AC CHARACTERISTICS (Commercial product:TA=0 to 70C, Extended product:TA=-25 to 85C, Industrial product: TA=-40 to 85C
K6T1008V2C Family: Vcc=3.0~3.6V, K6T1008U2C Family: Vcc=2.7~3.3V)
Speed Bins Parameter List Symbol 70ns Min Read cycle time Address access time Chip select to output Output enable to valid output Read Chip select to low-Z output Output enable to low-Z output Chip disable to high-Z output Output disable to high-Z output Output hold from address change Write cycle time Chip select to end of write Address set-up time Address valid to end of write Write Write pulse width Write recovery time Write to output high-Z Data to write time overlap Data hold from write time End write to output low-Z tRC tAA tCO1, tCO2 tOE tLZ tOLZ tHZ tOHZ tOH tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW 70 10 5 0 0 10 70 60 0 60 55 0 0 30 0 5 Max 70 70 35 25 25 25 Min 85 10 5 0 0 15 85 70 0 70 60 0 0 35 0 5 85ns Max 85 85 40 25 25 30 100ns Min 100 10 5 0 0 15 100 80 0 80 70 0 0 40 0 5 Max 100 100 50 30 30 30 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units
DATA RETENTION CHARACTERISTICS
Item Vcc for data retention Data retention current Data retention set-up time Recovery time Symbol VDR IDR tSDR tRDR CS11)Vcc-0.2V Vcc=3.0V, CS1Vcc-0.2V, CS2VCC-0.2V, or CS20.2V See data retention waveform Test Condition1) Min 2.0 0 5 Typ 0.3 Max 3.6 5 Unit V A ms
1. CS1Vcc-0.2V, CS2VCC-0.2V, or CS20.2V
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Revision 2.0 November 1997
K6T1008V2C, K6T1008U2C Family
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
tRC Address tOH Data Out Previous Data Valid tAA
CMOS SRAM
Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC Address tAA tCO1 CS1 tHZ(1,2) CS2 tCO2 tOE tOH
OE tOLZ tLZ Data Valid tOHZ
Data out
NOTES (READ CYCLE)
High-Z
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection.
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Revision 2.0 November 1997
K6T1008V2C, K6T1008U2C Family
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC Address tCW(2) CS1 tAW CS2 tCW(2) tWP(1) WE tAS(3) Data in tWHZ Data out Data Undefined tDW Data Valid tOW tDH tWR(4)
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled)
tWC Address tAS(3) CS1 tAW CS2 tWP(1) WE tDW Data in Data Valid tDH tCW(2) tWR(4)
Data out
High-Z
High-Z
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Revision 2.0 November 1997
K6T1008V2C, K6T1008U2C Family
TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)
tWC Address tAS(3) CS1 tAW CS2 tCW(2) tWP(1) tDW Data in Data Valid tDH tCW(2) tWR(4)
CMOS SRAM
WE
Data out
NOTES (WRITE CYCLE)
High-Z
High-Z
1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low, CS2 going high and WE going low: A write end at the earliest transition among CS1 going high, CS2 going low and WE going high, tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS1 going low or CS2 going high to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR(1) applied in case a write ends as CS1 or WE going high tWR(2) applied in case a write ends as CS2 going to low.
DATA RETENTION WAVE FORM
CS1 controlled
VCC 3.0/2.7V 1) tSDR Data Retention Mode tRDR
2.2V VDR CS1VCC-0.2V
CS1 GND
CS2 controlled
VCC 3.0/2.7V1) CS2 tSDR
Data Retention Mode
tRDR
VDR 0.4V GND
1. 3.0V for K6T1008V2C Family, 2.7V for K6T1008U2C Family
CS20.2V
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Revision 2.0 November 1997
K6T1008V2C, K6T1008U2C Family
PACKAGE DIMENSIONS
32 PIN PLASTIC SMALL OUTLINE PACKAGE (525mil)
CMOS SRAM
Units: millimeter(inch)
0~8 #32 #17
14.120.30 0.5560.012
11.430.20 0.4500.008
#1 20.87 0.822 MAX 20.470.20 0.8060.008
#16 2.740.20 0.1080.008 3.00 0.118 MAX
13.34 0.525
0.20 +0.10 -0.05 0.008+0.004 -0.002
0.800.20 0.0310.008
0.10 MAX 0.004 MAX
+0.100 -0.050 +0.004 0.016 -0.002
(
0.71 ) 0.028
0.41
1.27 0.050
0.05 MIN 0.002
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Revision 2.0 November 1997
K6T1008V2C, K6T1008U2C Family
PACKAGE DIMENSIONS
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F)
CMOS SRAM
Units: millimeter(inch)
0.20 0.008
+0.10 -0.05 +0.004 -0.002
13.400.20 0.5280.008 #32
#1
0.10 MAX 0.004
( 8.40 0.331 MAX 8.00 0.315
0.25 ) 0.010
0.50 0.0197
#16
#17 1.000.10 0.0390.004
0.25 TYP 0.010
11.800.10 0.4650.004
+0.10 -0.05 0.006 +0.004 -0.002
0.15
0.05 0.002 MIN 1.20 0.047 MAX
0~8
0.45~0.75 0.018~0.030
(
0.50 ) 0.020
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0813.4R)
0.10 MAX 0.004 0.20 0.008
+0.10 -0.05 +0.004 -0.002
13.400.20 0.5280.008 #17 ( 8.40 0.331 MAX 8.00 0.315 0.25 ) 0.010
#16
0.50 0.0197
#1 0.25 TYP 0.010
#32 1.000.10 0.0390.004 11.800.10 0.4650.004
+0.10 -0.05 0.006 +0.004 -0.002
0.15
0.05 0.002 MIN
1.20 0.047 MAX
0~8
0.45~0.75 0.018~0.030
(
0.50 ) 0.020
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Revision 2.0 November 1997
K6T1008V2C, K6T1008U2C Family
PACKAGE DIMENSIONS
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820F)
CMOS SRAM
Units: millimeter(inch)
0.20
+0.10 -0.05 0.008+0.004 -0.002
20.000.20 0.7870.008 #32 ( 8.40 0.331 MAX 8.00 0.315 0.25 ) 0.010
#1
0.50 0.0197
#16
#17 1.000.10 0.0390.004 1.20 0.047 MAX
+0.10 -0.05 0.006+0.004 -0.002
0.05 0.002 MIN
0.25 0.010 TYP
18.400.10 0.7240.004
0.15
0~8
0.45 ~0.75 0.018 ~0.030
(
0.50 ) 0.020
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820R)
0.20
+0.10 -0.05 0.008+0.004 -0.002
20.000.20 0.7870.008 #17 ( 8.40 0.331 MAX 8.00 0.315 0.25 ) 0.010
#16
0.50 0.0197
#1
#32 1.000.10 0.0390.004 1.20 0.047 MAX 0.05 0.002 MIN
0.25 0.010 TYP
18.400.10 0.7240.004
0~8
0.45 ~0.75 0.018 ~0.030
(
0.50 ) 0.020
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Revision 2.0 November 1997
0.10 MAX 0.004 MAX
+0.10 -0.05 0.006 +0.004 -0.002
0.15
0.10 MAX 0.004 MAX

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